The simulator uses the basic DLX architecture described in Hennessy & Patterson's textbook; a summary of the instruction set can be found online. The simulator extends the basic architcture by including additional instructions and CPU features to allow operating system implementation. In addition, the simulator implements devices that can be accessed by using memory mapped locations. In other words, accesses to certain fixed memory address do particular things like reading a character from the keyboard or sending a command to the (simulated) disk to read a block. These changes to the architecture are described in this page.
Table of contents
This implementation of DLX follows the basic DLX implementation quite closely. In fact, user programs written for the basic DLX will work fine in this version of DLX with one minor difference: this version of DLX does not do delayed branches.
The major changes in this version of DLX relate to operating system support. The changes include:
This version of the DLX architecture includes several special registers to allow the implementation of an operating system that includes features such as memory protection. The registers are summarized in the following table:
| Register | Use |
|---|---|
| irvec | Contains the address that the CPU jumps to when it gets an interrupt or trap. |
| cause | Contains a number corresponding to the cause of the most recent interrupt. User traps have bit 25 set, and interrupts and other exceptions have bit 25 clear. |
| status | Contains all of the status information for the CPU. The meanings of the individual bits are described later. |
| isr | Interrupt status register. This holds the contents of the status register at the time of the most recent interrupt or trap. |
| iar | Contains the address at which execution should be resumed after interrupt or trap processing. This is usually the instruction following the one where the interrupt was taken. |
| ir31 | Contains the contents of r31 immediately before the most recent interrupt. This allows the interrupt handler to overwrite r31 and use it for a scratch register without having to save any registers first. |
| ptbase | Base of the top level page table. |
| ptbits | Sizes of the pages pointed to by the level 1 and level 2 page tables. If this register contains 0xa00015 (10<<16+21), each L1 table entry points to a 221 byte "page" and each L2 table entry points to a 210 byte page. Thus, each L1 entry points to an L2 table with 221/210 = 211 entries, each of which points to a 210 byte page. The format of page table entries is described below. |
Special registers can be read or written by the movi2s and movs2i instructions, which are privileged — they can only be used in system mode.
The status register contains the following bit fields:
| Bit(s) | Mask | Meaning |
|---|---|---|
| 3:0 | 0xf | Interrupt level. There are up to 16 interrupt levels for the DLX processor, though the current implementation only includes two levels (0000 and 1111). |
| 5 | 0x20 | FP true flag. This bit is set by the FP conditional instructions and read by the bfpf and bfpt instructions. |
| 6 | 0x40 | System mode bit. If this bit is set, the CPU is in system mode. If clear, it's running in user mode. |
| 8 | 0x100 | If this bit is set, use a page table for user-mode accesses. The base and size information for the page table is in the special registers described above. |
| 9 | 0x200 | If this bit is set, use a software-loaded TLB for user-mode accesses. |
All of the fields may be read or written in system mode using the movi2s instruction. As with other special registers, the contents of the status register are normally unavailable to user programs. However, the FP true flag may be read and written by user instructions, though it may not be directly examined by any means other than testing it with bfpf or bfpt.
Page tables in the DLX architecture only translate accesses between 0 and 0x7fffffff; this is done so that the simulator doesn't have to deal with addresses that might appear negative. This translation only occurs when the CPU is running in user mode, and only when a translation mechanism is indicated by the appropiate bit in the status register. Otherwise, no translation is done and the virtual address is used as a physical address.
Individual page table entries in DLX consist of a physical address and two status bits: valid and dirty. The valid bit (bit 0) is set by the page table builder to indicate that the PTE is valid and points to real physical memory (or a page table, for two-level page tables). If the bit is 1, the entry is valid. If the bit is 0, the entry is invalid. The dirty bit (bit 1) is set by the CPU whenever the page pointed to by the PTE is written. It may be cleared by the operating system, but will never be cleared by the CPU.
The physical address in a PTE points to either the next level of page table or an actual physical page. If it points to a physical page, it must be aligned on an even page boundary - the lowest n bits (for a page size of 2n) are cleared before adding the offset within a page. This is not true for page tables - page tables may be placed anywhere in memory, and need not be aligned on page boundaries (though they must be aligned on word boundaries).
This implementation of DLX uses memory mapped I/O for basic devices including keyboard input, screen output, timer operation, and disk control. Though screen ouptut and disk access are available through simulator traps as well, use of memory mapped I/O addresses is a more realistic interface to hardware. Using this interface gives OS implementers a feel for the challenges involved with accessing real hardware.
DLX features a timer that counts down from an initial value to zero, interrupting the CPU when it reaches zero. The timer value is available at any time, and can be either read or written. Reading the timer doesn't affect its countdown, but writing the timer changes the countdown value to whatever value is written. This overrides any countdown in effect at the time; the countdown restarts at the new value.
The address of the timer value is XXXX, and the value placed into the cause register upon a timer interrupt is XXXX.